This invention relates to improved semiconductor devices, especially those wherein high switching speeds and low power dissipation are desirable, e.g., logic and memory elements.
Logic and memory devices that operate at high speeds and low power levels are very important for computer and other applications. This is becoming even more important as VLSI circuits, with 10,000 or more gates per chip, are being developed. In silicon integrated circuits, the low power logic is CMOS (Complementary Metal Oxide Semiconductor; see, e.g., Sze, Physics of Semiconductor Devices, J. Wiley & Sons, 1981; DiLorenzo et al, GaAs FET Principles and Technology, Artech House, 1982; and Electronic Circuits Discrete and Integrated, Schilling et al, McGraw Hill, 1979, which disclosures are entirely incorporated by reference herein.) Silicon CMOS circuits with power dissipations of about 1 microwatt/gate are possible. The sacrifice made for low power operation of silicon CMOS is speed. Typically, at 1 uW/gate, the Si-CMOS delay is .about. 1 .mu.sec/gate. The limiting factors are the carrier mobilities.
Other materials (such as gallium arsenide) offer higher speed (thus, smaller delays) but at greatly increased power consumption (Eden et al., "Integrated Circuits, a Case for GaAs", IEEE Spectrum, 12/83, 31ff, e.g., FIG. 1). The higher speed results from the fact that electron mobilities in GaAs are about 5000 cm.sup.2 /V-sec (at n=10.sup.17 cm.sup.-3) compared to only 600 cm.sup.2 /V-sec in silicon. As Eden et al shows, GaAs has been used to make some of the fastest logic devices ever made.
Complementary logic works well in silicon because electron and hole mobilities are similar, 600 and 300 cm.sup.2 /V-sec respectively. In GaAs (and other compound semiconductors) the electron and hole mobilities are quite different, e.g., 6000 and 250 cm.sup.2 /V-sec, respectively, in GaAs. As a result, conventional complementary GaAs logic would be only marginally faster than in silicon and creates a further complication wherein the area of the p-type device must be an order of magnitude larger than the n-type device to match currents (Zuleeg, et al, "Double Implanted GaAs Complementary J-FET's", IEEE, El. Dev. Lett. EDL-5, January 1984, p. 21, whose disclosure is incorporated by reference herein). In GaAs designs then, the complementary configuration is suggested only when a power dissipation reduction is necessary despite the lack of increased speed. If the hole mobilities were high in GaAs-like materials, then high-speed, low power complementary logic could be made.
As can be seen, there remains a need for semiconductor devices which have an improved power-delay product, i.e., have shorter delay times and lower power dissipations.